1. Field of the Invention
The present invention relates to a driving apparatus for a display. More particularly, the present invention relates to a driving apparatus for a display with an area reduced.
2. Description of the Related Art
Examples of general Flat Panel Displays (FPDs) are Active-Matrix Liquid Crystal Displays (AMLCDs) and Active-Matrix Organic Light Emitting Eiodes (AMOLEDs). In order for the FPDs to express a gray scale of 10 bits or more, Digital-to-Analog Converters (DACs) of 10 bits or more are required in Display Driver Integrated circuits (DDIs).
FIG. 1 is a block diagram showing a construction of a conventional flat panel display system. A pixel circuit 105 in a display panel is driven by a display driver Integrated Circuit (IC) 104. The display driver IC 104 is included of a column driver IC 102 and a row driver IC 103. In the display driver IC 104, the row driver IC 103 sequentially selects rows of the pixel circuit 105 and then the column driver IC 102 supplies a voltage or current corresponding to a gray scale to be expressed to each pixel. The output signals of the column driver IC 102 and the row driver IC 103 are controlled by a timing controller 101. A power source for driving the flat panel display system is supplied to a direct current (DC-DC) converter 100.
FIG. 2 is a block diagram illustrating a construction of the column driver IC 102 shown in FIG. 1. As shown in FIG. 2, the column driver IC 102, includes a shift register 200, a first latch unit 201, a second latch unit 202, a digital-to-analog converter 203, and an output unit 205. Furthermore, the column driver IC 102 can includes a reference voltage source 207 for generating and supplying a reference voltage to the digital-to-analog converter 203.
The reference voltage source 207 generates a positive gamma reference voltage and a negative gamma reference voltage, using a resistor string. The number (2N) of the reference voltage inputted to the digital-to-analog converter 203 is determined depending on the number (N) of digital bits of RGB (Red, Green, and Blue) signals outputted from the first latch unit 201. The resistor string included in the reference voltage source 207 has one in every column driver IC. The digital-to-analog converter 203 has one in every channel. Thus, the digital-to-analog converter 203 is an important factor for determining an area of a driving apparatus for display because the digital-to-analog converter 203 provides hundreds per column driver IC 102.
FIGS. 3 to 5 are schematic circuit diagrams illustrating a construction of a conventional 10-bit digital-to-analog converter.
FIG. 3 shows a construction of a conventional 10-bit digital-to-analog converter with two stages.
Referring to FIG. 3, a first stage of the 10-bit digital-to-analog converter includes a first resistor column 300, an 8-bit decoder 301, and a first switch unit 302. The resistor column 300 generates and supplies a reference voltage to the first switch unit 302. The first switch unit 302 selects a reference voltage corresponding to a high 8-bit data signal outputted from the 8-bit decoder 301. A second stage includes a middle buffer 303, a second resistor column 304, a 2-bit decoder 305, a second switch unit 306, and an output buffer 307. The middle buffer 303 serves to separate the first stage and the second stage. The second resistor column 304 divides a reference voltage selected in the first switch unit 302 and supplies the divided reference voltage to the second switch unit 306. The second switch unit 306 selects a reference voltage corresponding to a low 2-bit data signal outputted from the 2-bit decoder 305.
The 10-bit digital-to-analog converter of FIG. 3 reduces a circuit area to some degree compared to a typical 10-bit digital-to-analog converter, but has a drawback of not being able to guarantee the accuracy and uniformity of output because of an offset error of the middle buffer 303.
FIG. 4 is a circuit diagram illustrating a 10-bit digital-to-analog converter proposed in the treatise made public by Society for Information Display (SID) 2005.
In the 10-bit digital-to-analog converter of FIG. 4, the middle buffer 303 shown in FIG. 3 has been omitted. In the digital-to-analog converter of FIG. 4, the middle buffer 303 has been omitted to reduce an offset error, but a loading effect in which a resistor of a second stage has influence upon an output of a first stage is caused. To reduce the loading effect, a resistance value of the second stage should increase. This leads to an increase of an area of a column driver IC.
FIG. 5 is a circuit diagram illustrating a 10-bit digital-to-analog converter made public in Korean Patent Application No. 10-2004-0093227 filed Nov. 15, 2004.
Referring to FIG. 5A, a first stage of the 10-bit digital-to-analog converter includes a resistor column 500, an 8-bit decoder 501, and a first switch unit 502. A second stage includes an output buffer 505, a 2-bit decoder 503, and a second switch unit 504.
FIG. 5B is a circuit diagram showing the output buffer 505 of FIG. 5A. Referring to FIG. 5B, four positive input transistors 506 are all equal in size. A negative input transistor 507 is four times the positive input transistor 506 in size. The positive input transistors 506 receive one reference voltage corresponding to a low 2-bit data signal among reference voltages outputted from the first stage. The 10-bit digital-to-analog converter shown in FIG. 5A reduces a circuit area to some degree compared to a typical 10-bit digital-to-analog converter, but causes a reduction of the accuracy and uniformity of a signal outputted from the output buffer 505 because an offset error and non-linearity of the output buffer 505 has a direct influence upon operation of the 10-bit digital-to-analog converter shown in FIG. 5A. Further, an electric power consumption increases because the number of the positive input transistors connecting in parallel on the output buffer 505 should increase in order for the second switch unit 504 of the second stage to process a data signal of 3 bits or more.